AMD Spec for Easier Multithread Development
Advanced Micro Devices recently published a proposed specification for a new class of hardware extensions designed to increase the performance of applications running in multicore environments.
Dubbed "Light-Weight Profiling" (LWP), the specs are essentially an extension of AMD's x86 instruction set that provides more information to help developers optimize their programs as they're running on multicore machines, explained Earl Stahl, AMD's vice president of software engineering.
"Because of the way hardware has been changing and evolving -- and will continue to do so -- it's simply necessary for companies like ours to work with the greater ecosystem to ensure that the software will be able to exploit the features of the new hardware," Stahl said.
As AMD defines it,"light-weight profiling" is designed to enable code to make dynamic and real-time decisions about how best to improve the performance of concurrently running tasks. It utilizes such techniques as memory organization and code layout, with little overhead. These capabilities should work particularly well in runtime environments, Stahl said, such the Java Virtual Machine and the .NET CLR, which can run multiple threads and are used to develop an increasingly large percentage of applications.
"What AMD is saying is that it will be possible for developers to use these profiling techniques to capture and tune their programs in ways that are hard to do today," said Nathan Brookwood, research fellow at Insight64. "And by extending the x86 instruction set in subtle ways, AMD is providing more information to help developers optimize their programs as they are running."
AMD isn't the first chip maker to offer a helping hand to software developers and toolmakers coping with the complexities of the new multithreaded environments. In June, rival Intel introduced its C++ Compiler and Fortran Professional Edition, which combine highly optimizing compilers, performance libraries and the Intel Threading Building Blocks (TBB). The TBB is a library designed to help developers leverage multicore processor performance. According to Intel, the TBB "is not just a threads-replacement library. It represents a higher-level, task-based parallelism that abstracts platform details and threading mechanism for performance and scalability."
That the industry's two top makers of microprocessors are developing their own flavors of support for multithreaded development doesn't worry Brookwood.
"Sure, it would great if AMD and Intel got together on this, but I think the industry could sustain two slightly different directions here," he said, "just as the industry is sustaining variations in the way virtualization is being implemented in the two architectures. In fact, anything AMD, Intel, or anyone else can do to help developers create software that fully utilizes multicore environments is very welcome."
AMD is publishing the spec on its Developer Central Web site, and it is encouraging the software community to share feedback, comments and suggestions. The company calls this kind of presentation for public input "open innovation." Last year, AMD published its chip-level virtualization technology spec, code-named Pacifica, on the site.
This is the first specification released under the company's Hardware Extensions for Software Parallelism initiative. AMD plans to offer more extensions under that initiative for areas such as software transactional memory, high-performance message-passing, and fast context-switching for lightweight parallelism. All of these specs will be published for public review, Stahl said.
The LWP spec is now available here.
John K. Waters is the editor in chief of a number of Converge360.com sites, with a focus on high-end development, AI and future tech. He's been writing about cutting-edge technologies and culture of Silicon Valley for more than two decades, and he's written more than a dozen books. He also co-scripted the documentary film Silicon Valley: A 100 Year Renaissance, which aired on PBS. He can be reached at [email protected].